GSTF Journal on Computing (JoC)

, 3:46

First online:

Open Access This content is freely available online to anyone, anywhere at any time.

Comparative Analysis of 8-Bit Adder Cells Using CLRCL Full Adder Logic

  • Keshav KumarAffiliated withShaheed Bhagat Singh State Technical Campus
  • , Amit GroverAffiliated withShaheed Bhagat Singh State Technical Campus Email author 
  • , Neeti GroverAffiliated withShaheed Bhagat Singh State Technical Campus


In this paper, we propose a modified low power 10-T Adder design using 10 transistors & 12 transistors featuring higher computing speed, lower operating voltage, and lower energy consumption compared with peer designs. The simulation results, based on 0.18um process models, indicate that the proposed design has the lowest working Vdd and highest working frequency among all designs using 10 transistors & 12 transistors. It also features the lowest energy consumption per addition among these designs. In addition, the performance edge of the proposed design in both speed and energy consumption becomes even more significant as the word length of the adder increases.


Complementary & Level Restoring Full Adder Boolean Logic