Journal of Engineering Research

, 3:12

First online:

Open Access This content is freely available online to anyone, anywhere at any time.

Minimizing peak current in combinational circuit test

  • Mohammad G. Al-FailakawiAffiliated withComputer Engineering Department, Kuwait University Email author 
  • , Imtiaz AhmadAffiliated withComputer Engineering Department, Kuwait University


In the very large scale integration (VLSI) era, where millions of transistors are packed in a single chip, the demand for proper power management is of paramount importance. Low power test is taking center stage for both combinational and sequential circuits in recent years due to its impact on overall yield. This paper proposes a technique that targets the reduction of peak current during combinational circuit test to realize peak power reduction. Unlike previous methods, this approach utilizes peak current defined by the direction of switching activity to find minimum peak power. The proposed framework consists of two main phases, where the test set is first reordered using a combined peak current/peak power cost function followed by an x-refilling technique based on Fiduccia-Mattheyses algorithm to refill unspecified bit values. Experimental results on ISCAS85 benchmark circuits show that the proposed approach reduces peak current, peak power, and total power by 33%, 32%, and 43% respectively compared to Hamming distance-based ordering with random filling.


Circuit testing logic circuit low power optimization vector ordering